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High Efficiency Dual Output Power Supply Controller ADP3025
FEATURES
Wide input voltage range: 5.5 V to 25 V High conversion efficiency > 96% Integrated current sense--no external resistor required Low shutdown current: 19 A (typical) Voltage mode PWM with input feed-forward for fast line transient response Dual synchronous buck controllers Built-in gate drive boost circuit for driving external high-side N-channel MOSFET 2 independently programmable output voltages: Fixed 3.3 V or adjustable (800 mV to 6.0 V) Fixed 5 V or adjustable (800 mV to 6.0 V) Programmable PWM frequency Integrated linear regulator controller Extensive circuit protection functions
GENERAL DESCRIPTION
The ADP3025 is a highly efficient, dual synchronous buck switching regulator controller optimized for converting a battery or adapter input into the supply voltage required in portable products and industrial systems. The oscillator frequency can be programmed for 200 kHz or 300 kHz operation, or can be synchronized to an external clock signal of up to 350 kHz. The ADP3025 provides accurate and reliable short-circuit protection by using an internal current sense circuit that reduces cost and increases overall efficiency. Other protection features include programmable soft start, UVLO, and integrated output undervoltage/overvoltage protection. The ADP3025 contains a linear regulator controller designed to drive an external N-channel MOSFET. The linear regulator output is adjustable and can be used to generate auxiliary supply voltages. The ADP3025 is specified over the 0C to 70C commercial temperature range and is available in a 38-lead TSSOP package.
APPLICATIONS
Portable instruments General-purpose dc-to-dc converters
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
VIN 5.5V TO 25V PFO 5V LINEAR REGULATOR REF Q1 L1 5V SWITCHING CONTROLLER 3.3V SWITCHING CONTROLLER 3.3V Q2 800mV
Q3 L2 5V Q4
SS5
SS3
Q5 LINEAR CONTROLLER POWER-ON RESET
PWRGD
2.5V
ADP3025
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
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ADP3025 TABLE OF CONTENTS
Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 9 Theory of Operation ...................................................................... 11 Internal 5 V Supply (INTVCC) ................................................ 11 Reference (REF).......................................................................... 11 Boosted High-Side Gate Drive Supply (BST) ......................... 11 Synchronous Rectifier (DRVL) ................................................ 11 Oscillator Frequency and Synchronization (SYNC).............. 11 Shutdown SD............................................................................... 11 Soft Start and Power-Up Sequencing (SS) .............................. 11 Current Limiting (CLSET) ........................................................ 12 Output Undervoltage Protection.............................................. 12 Output Overvoltage and Reverse Voltage Protection............ 12 Power Good Output (PWRGD) ............................................... 12 Linear Regulator Controller...................................................... 12 Output Voltage Adjustment ...................................................... 13 Application Information ........................................................... 13 Input Voltage Range ................................................................... 13 Maximum Output Current and MOSFET Selection ............. 14 Nominal Inductor Value............................................................ 15 Inductor Selection ...................................................................... 15 CIN and COUT Selection ............................................................... 16 Power MOSFET Selection......................................................... 16 Soft Start ...................................................................................... 17 Fixed or Adjustable Output Voltage......................................... 17 Efficiency Enhancement............................................................ 17 Transient Response Considerations......................................... 18 Feedback Loop Compensation................................................. 18 Compensation Loop Design and Test Method ...................... 19 Recommended Applications..................................................... 19 Layout Considerations............................................................... 19 Outline Dimensions ....................................................................... 21 Ordering Guide .......................................................................... 21
REVISION HISTORY
Revision A 4/04--Data Sheet changed from Rev. 0 to Rev. A Change Page
Changes to Features...................................................................... 1 Changes to Specifications ............................................................ 3 Changes to Figures 4 and 5.......................................................... 9 Changes to Theory of Operation section ................................ 11 Changes to Output Voltage Adjustment section .................... 13 Changes to Table 5...................................................................... 13 Changes to Table 6...................................................................... 15 Changes to Table 8...................................................................... 16 Changes to Table 9...................................................................... 17 1/04--Revision 0: Initial Version
Rev. A | Page 2 of 24
ADP3025 SPECIFICATIONS1
Table 1. TA = 0C to 70C, VIN = 12 V, SS5 = SS3 = INTVCC, INTVCC Load = 0 mA, REF Load = 0 mA, SYNC = 0 V, SD = 5 V, unless otherwise noted
Parameter INTERNAL 5 V REGULATOR Input Voltage Range Output Voltage Line Regulation Total Variation VIN Undervoltage Lockout Threshold Voltage Hysteresis REFERENCE Output Voltage2 SUPPLY Shutdown Current Standby Current Quiescent Current Symbol INTVCC Conditions Min 5.5 4.95 4.8 4.05 4.25 270 800 19 120 1.3 Typ Max 25 5.15 5.2 4.5 Unit V V mV/V V V mV mV A A mA
VUVLO
TA = 25C 5.5 V VIN 25 V Full VIN and temperature range INTVCC falling
5.02 1.0
REF IQ
5.5 V VIN 25 V 5.5 V VIN 25 V, SD= 0 V SS3 = SS5 = COMP2/SD2 = 0 V, SD = 5 V No loads, SS3 = SS5 = COMP2/SD2 = 4 V, FB5 = 810 mV, FB3 = 810 mV, FB2 = 810 mV, ADJ/FX5 = ADJ/FX3 = 5 V
784
816 70 200 1.9
OSCILLATOR Frequency SYNC Input Frequency Range Input Low Voltage3 Input High Voltage3 Input Current POWER GOOD Output Voltage in Regulation Output Voltage out of Regulation PWRGD Trip Threshold PWRGD Hysteresis CPOR Pull-Up Current ERROR AMPLIFIER DC Gain3 Gain-Bandwidth Product3 Input Leakage Current
fOSC
SYNC = AGND, 5.5 V VIN 25 V SYNC = INTVCC, 5.5 V VIN 25 V
175 250 230
210 300
245 350 350 0.4
kHz kHz kHz V V A V V % % A dB MHz nA
tF 200 ns tR 200 ns SYNC = 5 V PWRGD 10 k pull-up to 5 V 10 k pull-up to 5 V, FB5 < 90% of nominal output value FB5 rising; with respect to nominal output FB5 falling; with respect to nominal output CPOR = 1.2 V
2.8 0.5 4.8 0.4 -6.0 -3.0 -3.7 4 -1 47 10 -1.5 -0.3
GBW IEAN
ADJ/FX5 = ADJ/FX3 = 5 V
200
Rev. A | Page 3 of 24
ADP3025
SPECIFICATIONS (continued)
Parameter MAIN SMPS CONTROLLERS Fixed 5 V Output Voltage Fixed 3.3 V Output Voltage Adjustable Output Voltage Output Voltage Adjustment Range3 Current Limit Threshold CLSET5 = CLSET3 = Floating CLSET5 = CLSET3 = 0 V Soft Start Current Soft Start Turn-On Threshold Feedback Input Leakage Current Maximum Duty Cycle3 Transition Time (DRVL) Rise Fall Transition Time (DRVH) Rise Fall Logic Input Voltage ADJ/FX3, ADJ/FX5, SD Logic Low Logic High LINEAR REGULATOR CONTROLLER Feedback Threshold COMP2/SD2 Pull-Up Current COMP2/SD2 Threshold DC Gain3 Transconductance gm 3 Gain-Bandwidth Product3 FB2 Input Leakage Current POWER-FAIL COMPARATOR PFI Input Threshold PFI Input Hysteresis PFI Input Current PFO High Voltage PFO Low Voltage FAULT PROTECTION Output Overvoltage Trip Threshold Output Undervoltage Lockout Threshold Symbol FB5 FB3 FB5, FB3 Conditions 5.5 V VIN 25 V, ADJ/FX5 = 0 V 5.5 V VIN 25 V, ADJ/FX3 = 0 V 5.5 V VIN 25 V, ADJ/FX5 = ADJ/FX3 = 5 V ADJ/FX5 = ADJ/FX3 = 5 V 5.5 V = VIN = 25 V, TA = 25C 5.5 V VIN 25 V, TA = 25C SS3 = SS5 = 3 V SS5, SS3 IFB DMAX tR(DRVL) tF(DRVL) tR(DRVH) tF(DRVH) ADJ/FX5 = ADJ/FX3 = 5 V, FB = 800 mV VIN = 5.5 V, SYNC = AGND CLOAD = 3000 pF, 10% to 90% CLOAD = 3000 pF, 90% to 10% CLOAD = 3000 pF, 10% to 90% CLOAD = 3000 pF, 90% to 10% Min 4.90 3.234 776 0.800 54 240 0.7 0.4 94 72 300 2.1 0.6 99 40 45 50 50 70 70 100 100 Typ 5.0 3.3 800 Max 5.10 3.366 824 6.0 90 360 3.8 0.8 600 Unit V V mV V mV mV A V nA % ns ns ns ns
VIL VIH FB2 COMP2/SD2
0.6 2.9 776 COMP2/SD2 = 0 V 0.5 COMP2/SD2 = 3 V 800 2.8 0.85 62 0.3 20 20 800 14 824 1.1
V V mV A V dB ms MHz nA mV mV nA V V % %
GBW IFB2 PFI IPFI PFOH PFOL
FB2 = 800 mV PFO from high to low 776
824 500
10 k pull-up to 5 V 10 k pull-up to 5 V With respect to nominal output With respect to nominal output
4.8 0.4 115 70 120 80 125 90
1 2 3
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods. The reference's line regulation error is insignificant. The reference is not supposed to be loaded externally. Guaranteed by design, not tested in production.
Rev. A | Page 4 of 24
ADP3025 ABSOLUTE MAXIMUM RATINGS
Table 2. ADP3025 Stress Ratings
Parameter VIN to AGND AGND to PGND INTVCC BST5, BST3 to PGND BST5 to SW5 BST3 to SW3 CS5, CS3 SW3, SW5 to PGND SD DRVL5/3 to PGND DRVH5/3 to SW5/3 All Other Inputs and Outputs JA Operating Ambient Temperature Range Junction Temperature Range Storage Temperature Range Lead Temperature Range (Soldering 10 sec) Rating -0.3 V to +27 V 0.3 V AGND - 0.3 V to +6 V -0.3 V to +32 V -0.3 V to +6 V -0.3 V to +6 V AGND - 0.3 V to VIN -2 V to VIN + 0.3 V AGND - 0.3 V to +27 V -0.3 V to INTVCC + 0.3 V -0.3 V to INTVCC + 0.3 V AGND - 0.3 V to INTVCC + 0.3 V 98C/W 0C to 70C 0C to 150C -65C to +150C 300C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 5 of 24
ADP3025 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CS5 1 FB5 2 EAN5 3 EAO5 4 ADJ/FX5 5 SS5 6 CLSET5 7 REF 8 38 BST5 37 DRVH5 36 SW5 35 DRVL5 34 PGND1 33 S D
ADP3025
32 PGND2
TOP VIEW 31 INTVCC1 (Not to Scale) 30 VIN AGND 9 CLSET3 10 INTVCC2 11 SYNC 12 SS3 13 ADJ/FX3 14 EAO3 15 EAN3 16 FB3 17 CS3 18 PFI 19 29 DRVL3 28 SW3 27 DRVH3 26 BST3 25 DRV2 24 FB2 23 COMP2/SD2 22 CPOR
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21 PWRGD 20 PFO
Figure 2. 38-Lead TSSOP Pin Configuration
Table 3. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11, 31 12 13 14 15 16 17 18 Mnemonic CS5 FB5 EAN5 EAO5 ADJ/FX5 SS5 CLSET5 REF AGND CLSET3 INTVCC2, 1 SYNC SS3 ADJ/FX3 EAO3 EAN3 FB3 CS3 Function Current Sense Input for the Top N-Channel MOSFET of the 5 V Buck Converter. Connect to the drain of the top N-channel MOSFET. Feedback Input for the 5 V Buck Converter. Connect to the output sense point in fixed output mode. Connect to an external resistor divider in adjustable output mode. Inverting Input of the Error Amplifier of the 5 V Buck Converter. Use for external loop compensation only in fixed output mode. In adjustable output mode, connect to the external resistor divider. Error Amplifier Output for the 5 V Buck Converter. TTL Logic Input. When ADJ/FX5 = 0 V, fixed output mode, connect FB5 to the output sense point. When ADJ/FX5 = 5 V, adjustable output mode, connect FB5 to the external resistor divider. Soft Start for the 5 V Buck Converter. Also used as an ON/OFF pin. Current Limit Setting. A resistor can be connected from AGND to CLSET5. A minimum current limit is obtained by leaving it open. A maximum current limit is obtained by connecting it to AGND. 800 mV Reference. Bypass it with a capacitor (22 nF typical) to AGND. REF cannot be loaded externally. Analog Signal Ground. Current Limit Setting. A resistor can be connected from AGND to CLSET3. A minimum current limit is obtained by leaving it open. A maximum current limit is obtained by connecting it to AGND. Linear Regulator Bypass for the Internal 5 V LDO. Bypass this pin with a 4.7 F capacitor to AGND. Pins 11 and 31 must be connected for proper operation. Oscillator Synchronization and Frequency Select. fOSC = 200 kHz when SYNC = 0 V; select fOSC = 300 kHz, when SYNC = 5 V. The oscillator can be synchronized with an external source through the SYNC pin. Soft Start for the 3.3 V Buck Converter. Also used as an ON/OFF pin. TTL Logic Input. When ADJ/FX3 = 0 V, fixed output mode, connect FB3 to the output sense point. When ADJ/FX3 = 5 V, adjustable output mode, connect FB3 to the external resistor divider. Error Amplifier Output for the 3.3 V Buck Converter. Error Amplifier Inverting Input of the 3.3 V Buck Converter. Use for external loop compensation only in fixed output mode. In adjustable output mode, connect to an external resistor divider. Feedback Input for the 3.3 V Buck Converter. Connect to output sense point in fixed output mode. Connect to an external resistor divider in adjustable output mode. Current Sense Input for the Top N-Channel MOSFET of the 3.3 V Buck Converter. CS3 should be connected to the drain of the N-channel MOSFET.
Rev. A | Page 6 of 24
ADP3025
Pin No. 19 20 21 Mnemonic PFI PFO PWRGD Function Negative Input of a Comparator that can be Used as a Power-Fail Detector. The positive input is connected to the 800 mV reference. There is a 14 mV hysteresis for this comparator. Power Failure Output, Open Drain Output. This pin sinks current when the PFI pin is lower than 800 mV. Otherwise, PFO is floating. Power Good Output. PWRGD goes low with no delay whenever the 5 V output drops 7% below its nominal value. When the 5 V output is within -3% of its nominal value, PWRGD is released after a time delay determined by the timing capacitor on the CPOR pin. Power-On Reset Capacitor. Connect a capacitor between CPOR and AGND to set the delay time for the PWRGD pin. A 1 A pull-up current is used to charge the capacitor. A manual reset (MR) function can also be achieved by pulling this pin low. Compensation Input for the Linear Regulator Controller. Connect an RC network to GND for stable operation. This pin is also used as an ON/OFF pin of the linear regulator controller. Feedback for the Linear Regulator Controller. NMOS Gate Drive Output for the Linear Regulator Controller. Boost Capacitor Connection for High-Side Driver of the 3.3 V Buck Converter. High-Side Gate Drive for the 3.3 V Buck Converter. Switching Node (Inductor) Connection of the 3.3 V Buck Converter. Low-Side Gate Drive of the 3.3 V Buck Converter. Main Supply Input (5.5 V to 25 V). Power Ground. Pins 32 and 34 must be connected together for proper operation. Shutdown Control Input, Active Low. If SD = 0 V, the chip is in shutdown mode with very low quiescent current. For automatic startup, connect SD to VIN via a resistor. Low-Side Gate Drive for the 5 V Buck Converter. Switching Node (Inductor) Connection for the 5 V Buck Converter. High-Side Gate Drive for the 5 V Buck Converter. Boost Capacitor Connection for the High-Side Driver of the 5 V Buck Converter.
22
CPOR
23 24 25 26 27 28 29 30 32, 34 33 35 36 37 38
COMP2/SD2 FB2 DRV2 BST3 DRVH3 SW3 DRVL3 VIN PGND2, 1 SD DRVL5 SW5 DRVH5 BST5
Rev. A | Page 7 of 24
ADP3025
INPUT PGND VIN 30
ADP3025
OC
+ - SD 33 INTVCC1 5V 31 11 INTVCC2 REF AGND 8 +5V LINEAR REG + -
72mV -+
CS5 1
14mV -+ CLSET5 7
800mV REF
UVLO
9 38 - 0.8V + INTVCC 37 36 200kHz/ 300kHz/ OSC BST5 DRVH5 SW5 VOUT5 5V
PFO 20 PFI 19
SYNC 12 PWRGD 21
CONTROL LOGIC
35 34
DRVL5 PGND1 PGND2
POWERON RESET
1A
FB5 + - -3mV
32
3.3V
CPOR
22 + -
816mV
2
FB5
DRV2 25 2.5V FB2 24 0.8V COMP2/SD2 - gm + + - x1 + - - 792mV EAN5 800mV
SHUTDOWN
S Q R
OC 1.8V -
-
DUPLICATE FOR SECOND CONTROLLER
Figure 3. Block Diagram (All Switches and Components Shown for Fixed Output Operation)
Rev. A | Page 8 of 24
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+
+ + - + - +
23
EA
800mV
3
4 960mV
EAO5
5 ADJ/FX5 0.7A 640mV
2.1A 6
SS5
0.6V
ADP3025 TYPICAL PERFORMANCE CHARACTERISTICS
100
190
80 VIN = 6.5V
EFFICIENCY (%)
VIN = 15V
170 150
60
CURRENT (A)
130 +70C 110 +25C 90 0C 70
40
20
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0
1
2 OUTPUT CURRENT (A)
3
4
5
10
15 INPUT VOLTAGE (V)
20
25
Figure 4. Efficiency vs. 5 V Output Current
Figure 7. Input Standby Current vs. Input Voltage
100
70
80 VIN = 6.5V 60
VIN = 15V
60 50
EFFICIENCY (%)
CURRENT (A)
40
40
30
20
20
10
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0
1
2 OUTPUT CURRENT (A)
3
4
5
10
15 INPUT VOLTAGE (V)
20
25
Figure 5. Efficiency vs. 3.3 V Output Current
Figure 8. Input Shutdown Current vs. Input Voltage
1800
310
VIN=25V 1600 305
+70C 1400 +25C 0C 1200
FREQUENCY (kHz)
VIN=12V
CURRENT (A)
300
295 VIN=7.5V VIN=5.5V
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5
10
15 INPUT VOLTAGE (V)
20
25
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1000
290 0 10 20 30 40 50 60 70 AMBIENT TEMPERATURE (C)
Figure 6. Input Current vs. Input Voltage
Figure 9. Oscillator Frequency vs. Temperature
Rev. A | Page 9 of 24
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0
0
02699-0-007
0
50
ADP3025
400 CLSET = GND 350 VIN = 5.5V TO 25V
CURRENT LIMIT THRESHOLD (mV)
300
250
0
10
20
30
40
50
60
70
AMBIENT TEMPERATURE (C)
Figure 10. Current Limit Threshold vs. Temperature
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200
Figure 13. Load Transient Response--1 A to 3 A
816 812
REFERENCE OUTPUT (mV)
808 804 800 796 792 788
02699-0-011
784 0 10 20 30 40 50 60 70 AMBIENT TEMPERATURE (C)
Figure 11. Reference Output vs. Temperature
Figure 14. Load Transient Response--3 A to 1 A
Figure 12. Soft Start Sequencing
Figure 15. VIN = 7.5 V to 22 V Transient, 2.5 V Output, CH1--Input Voltage, CH2--Output Voltage
Rev. A | Page 10 of 24
ADP3025 THEORY OF OPERATION
The ADP3025 contains two synchronous step-down buck controllers and a linear regulator controller. The buck controllers in the ADP3025 have the ability to provide either fixed 3.3 V and 5 V outputs or independently adjustable (800 mV to 6.0 V) outputs. Efficiency is improved by eliminating the external current sense resistor, which is the main contributor to loss during high current, low output voltage conditions. cross-conduction during switch transitions. The low-side driver must be turned off before the high-side driver is turned on. For typical N-channel MOSFETs, the dead time is approximately 50 ns. On the other edge, a dead time of approximately 50 ns is achieved by an internal delay circuit. In discontinuous conduction mode (DCM), the synchronous rectifier is turned off when the current flowing through the low-side MOSFET falls to zero. In continuous conduction mode (CCM), the current flowing through the low-side MOSFET never reaches zero, so the synchronous rectifier is turned off by the next clock cycle.
INTERNAL 5 V SUPPLY (INTVCC)
An internal low dropout regulator (LDO) generates a 5 V supply (INTVCC) that powers all the functional blocks within the IC. The total current rating of this LDO is 50 mA. However, this current is used for supplying gate drive power; current should not be drawn from this pin for other purposes. Bypass INTVCC to AGND with a 4.7 F capacitor. A UVLO circuit is also included in the regulator. When INTVCC < 4.05 V, the two switching regulators and the linear regulator controller are shut down. The UVLO hysteresis voltage is about 300 mV. The internal LDO has a built-in foldback current limit so that it is protected if a short circuit is applied to the 5 V output.
OSCILLATOR FREQUENCY AND SYNCHRONIZATION (SYNC)
The SYNC pin controls the oscillator frequency. When SYNC = 0 V, fOSC = 200 kHz; when SYNC = 5 V, fOSC = 300 kHz. 300 kHz operation minimizes external component size and cost; 200 kHz operation provides better efficiency and lower dropout. The SYNC pin can also be used to synchronize the oscillator with an external 5 V clock signal. A low-to-high transition on SYNC initiates a new cycle. The synchronization range is 230 kHz to 350 kHz.
REFERENCE (REF)
The ADP3025 contains a precision 800 mV reference. Bypass REF to AGND with a 22 nF ceramic capacitor. The reference is intended for internal use only.
SHUTDOWN SD
Holding SD low puts the ADP3025 into ultralow current shutdown mode. For automatic startup, SD can be tied to VIN via a resistor.
BOOSTED HIGH-SIDE GATE DRIVE SUPPLY (BST)
The gate drive voltage for the high-side N-channel MOSFET is generated by a flying-capacitor boost circuit. The boost capacitor connected between BST and SW is charged from the INTVCC supply. Use only small-signal diodes for the boost circuit.
SOFT START AND POWER-UP SEQUENCING (SS)
SS3 and SS5 are soft start pins for the two controllers. A 2 A pull-up current is used to charge an external soft start capacitor. Power-up sequencing can easily be done by choosing different capacitance. When SS3/SS5 < 0.6 V, the two switching regulators are turned off. When 0.6 V < SS5/SS3 < 1.8 V, the regulators start working in soft start mode. When SS3/SS5 > 1.8 V, the regulators are in normal operating mode. The minimum soft start time (~20 s) is set by an internal capacitor. Table 4 shows the ADP3025 operating modes.
SYNCHRONOUS RECTIFIER (DRVL)
Synchronous rectification is used to reduce conduction losses and ensure proper startup of the boost gate driver circuit. Antishoot-through protection has been included to prevent
Table 4. Operating Modes
SD Low High High High High High SS5 SS5 < 0.6 V 0.6 V < SS5 < 1.8 V 1.8 V < SS5 SS3 SS3 < 0.6 V Description All Circuits Turned Off 5 V and 3.3 V Off; INTVCC = 5 V, REF = 800 mV 5 V in Soft Start 5 V in Normal Operation 3.3 V in Soft Start 3.3 V in Normal Operation
0.6 V < SS3 < 1.8 V 1.8 V < SS3
Rev. A | Page 11 of 24
ADP3025
CURRENT LIMITING (CLSET)
A cycle-by-cycle current limiting scheme is used by monitoring current through the top N-channel MOSFET when it is turned on. By measuring the voltage drop across the high-side MOSFET, VDS(ON), the use of an external sense resistor can be omitted. The current limit value can be set by CLSET. When CLSET is floating, the maximum VDS(ON) = 72 mV at room temperature; when CLSET = 0 V, the maximum VDS(ON) = 300 mV at room temperature. An external resistor can be connected between CLSET and AGND to choose a value between 72 mV and 300 mV. The relationship between the external resistance and the maximum VDS(ON) is
VDS (ON ) MAX = 72 mV (110 k + REXT ) (26 k + REXT )
POWER GOOD OUTPUT (PWRGD)
The ADP3025 also provides a PWRGD signal output. During startup, the PWRGD pin is held low until the 5 V output is within -3% of its preset voltage. Then, after a time delay determined by an external timing capacitor connected from CPOR to GND, PWRGD is actively pulled up to INTVCC by an external pull-up resistor. This delay can be calculated by
tD =
1.2 V x CCPOR 1 A
(2)
(1)
CPOR can also be used as a manual reset (MR) input. When the 5 V output is lower than the preset voltage by more than 7%, PWRGD is immediately pulled low.
LINEAR REGULATOR CONTROLLER
The ADP3025 includes an on-board linear regulator controller. An external NMOS can be used as the pass transistor. The output voltage can be set by a resistor divider. The minimum output voltage of the LDO is 800 mV, while the maximum output voltage cannot exceed a voltage level determined by the IC's INTVCC voltage minus the threshold voltage of the external N-type MOSFET device. Assuming a INTVCC of 5 V, the recom-mended maximum output voltage is around 2.5 V. To ensure loop stability, a compensation network can be attached to the COMP2/SD2 pin, as shown in Figure 17. Large signal response limits the maximum/minimum load ratio. When the linear regulator is loaded, the MOSFET's gate source voltage is at its threshold level and changes only slightly. The loop response speed depends on the loop transfer function, which is fast enough for most applications. However, when the load is extremely light, the gate source voltage of the MOSFET is much lower than its nominal value. If at this moment the load increases suddenly, the MOSFET's gate source capacitance needs to be charged up, which takes time. To optimize large signal response, not exceeding a maximum-to-minimum load ratio of 100 to 1 is recommended.
The temperature coefficient of RDS(ON) of the N-channel MOSFET is canceled by the internal current limit circuitry, so an accurate current limit value can be obtained over a wide temperature range.
OUTPUT UNDERVOLTAGE PROTECTION
Each switching controller has an undervoltage protection circuit. When the current flowing through the high-side MOSFET reaches the current limit continuously for eight clock cycles and the output voltage stays below 20% of the nominal output voltage, both controllers are latched off and do not restart until SD or SS3/SS5 is toggled, or until VIN is cycled below 4.05 V. This feature is disabled during soft start.
OUTPUT OVERVOLTAGE AND REVERSE VOLTAGE PROTECTION
Both converter outputs are continuously monitored for overvoltage. If either output voltage is higher than the nominal output voltage by more than 20%, both converters' high-side gate drivers (DRVH5/3) are latched off, and the low-side gate drivers are latched on. The chip will not restart until SD or SS5/SS3 is toggled, or until VIN is cycled below 4.05 V. The lowside gate driver (DRVL) is kept high when the controller is in the off-state and the output voltage is less than 93% of the nominal output voltage. Discharging the output capacitors through the main inductor and low-side N-channel MOSFET causes the output to ring. This makes the output go below GND momentarily. To prevent damage to the circuit, use a 1 A Schottky diode in parallel with the output capacitors to clamp the negative surge.
Rev. A | Page 12 of 24
ADP3025
OUTPUT VOLTAGE ADJUSTMENT
Fixed output voltages (5 V/3.3 V) are selected when ADJ/FX5 = ADJ/FX3 = 0 V. The output voltage of each controller can also be set by an external feedback resistor network when ADJ/FX5 = ADJ/FX3 = 5 V, as shown in Figure 16. There should be two external feedback resistor dividers for each controller, one for the voltage feedback loop and one for the output voltage monitor. Both resistor dividers must be identical. The minimum output voltage is 800 mV, and the maximum output voltage is 6.0 V.
VIN
APPLICATION INFORMATION
A typical application circuit using the ADP3025 is shown in Figure 17. Although the component values given in Figure 17 are based on a 5 V @ 4 A/3.3 V @ 4 A/2.5 V @ 1.5 A design, the ADP3025 output drivers are capable of handling output currents anywhere from <1 A to over 10 A. Throughout this section, design examples and component values are given for three different power levels. For simplicity, these levels are referred to as low power and basic power. Table 5 shows the input/output specifications for these three levels.
Table 5. Typical Power Level Examples
Input Voltage Range Switching Output 1 Switching Output 2 Linear Output Low Power 5.5 V to 25 V 3.3 V/2 A 5 V/2 A 2.5 V/1 A Basic 5.5 V to 25 V 3.3 V/4 A 5 V/4 A 2.5 V/1.5 A
DRVH VOUT DRVL
ADP3025
R3 FB R4 EAN 5V ADJ/FX
02699-0-017
R1 R2
INPUT VOLTAGE RANGE
The input voltage range of the ADP3025 is 5.5 V to 25 V. The converter design is optimized to deliver the best performance within a 7.5 V to 18 V range, which is the nominal voltage for three to four cell Li-Ion battery stacks. Voltages above 18 V may occur under light loads and when the system is powered from an ac adapter with no battery installed.
Figure 16. Adjustable Output Mode
The output voltage can be calculated using the following formula:
R1 VOUT = 800 mV x 1 + R2
where R1/R2 = R3/R4.
(3)
If the loop is carefully compensated, R3 and R4 can be removed and FB and EAN can be tied together.
Rev. A | Page 13 of 24
ADP3025
VIN 5.5V-25V C22 4.7F R14 4.7
C18 150pF R10 10k
1 CS5 2 FB5 R1 130k C2 330pF 3 EAN5 4 EAO5
U1 ADP3025
BST5 38
C14A 10F C17 100nF D6 1N4148 Q5 SI4410
C14B 10F L2 6.8H D2 10BQ040 D4 10BQ040 ++ C27A 68F C27B 68F VOUT5 5V, 4A
DRVH5 37 SW5 36 DRVL5 35 PGND1 34 SD 33 PGND2 32 INTVCC1 31 VIN 30 DRVL3 29 SW3 28 DRVH3 27 BST3 26 DRV2 25 FB2 24 COMP2/SD2 23 CPOR 22 PWRGD 21 PFO 20
C1 68pF
5 ADJ/FX5 6 SS5 7 CLSET5 8 REF 9 AGND 10 CLSET3 11 INTVCC2 12 SYNC 13 SS3 14 ADJ/FX3 15 EAO3 16 EAN3 17 FB3 18 CS3 19 PFI
Q4 SI4410 R27 10k
C4 33nF
R2 200k
C5 22nF R3 200k
R5 10
C15 4.7F
D5 1N4148
C13 1F
C20A 10F
C20B 10F
C6 33nF
Q2 C12 SI4410 100nF
L1 6.8H D1 10BQ040 D3 10BQ040 ++ C24A 100F C24B 100F VOUT33 3.3V, 4A
C8 R4 75k 470pF C9 68pF
Q3 SI4410
C26 4.7F
Q1 IRF7403 R8 25.5k
VOUT25 2.5V, 1.5A C11 33F
C19 330pF R11 6.2k
R12 10k
C10 47nF PWRGD
R13 10k PFO
R26 34.8k
R24 200k
R9 49.9k C29 330pF
C28 33pF
R7 12k
Figure 17. 45 W, Triple Output DC-to-DC Converter
MAXIMUM OUTPUT CURRENT AND MOSFET SELECTION
The maximum output current for each switching regulator is limited by sensing the voltage drop between the drain and source of the high-side MOSFET when it is turned on. A current sense comparator senses voltage drop between CS5 and SW5 for the 5 V converter and between CS3 and SW3 for the 3.3 V converter. The sense comparator threshold is 72 mV when the programming pin CLSET is floating, and 300 mV when CLSET is connected to ground. Current limiting is based on sensing the peak current. Peak current varies with input voltage and depends on the inductor value. The higher the ripple current or input voltage, the lower the converter maximum output current at the set current sense amplifier threshold. The relation between peak and dc output current is given by
VIN ( MAX ) - VOUT IPEAK = IOUT + VOUT x 2 x f x L x VIN ( MAX )
At a given current comparator threshold, VTH and MOSFET RDS(ON), the maximum inductor peak current is
IPEAK = VTH RDS (ON )
Rearranging Equation 2 to solve for IOUT(MAX) gives IOUT ( MAX ) = VIN ( MAX ) - VOUT VTH - VOUT x 2 x f x L x VIN ( MAX ) RDS(ON ) (6)
VTH can be chosen to accommodate IOUT(MAX).
Rev. A | Page 14 of 24
02699-0-018
(4)
(5)
ADP3025
This current limit circuit is designed to protect against high current or short-circuit conditions only. This protects the IC and MOSFETs long enough to allow the output undervoltage protection circuitry to latch off the supply. Optimum standard inductor values for various output voltage and current levels are shown in Table 6.
Table 6. Standard Inductor Values
Frequency (kHz) 200 300 3.3 V/2 A 20 H 12 H 3.3 V/4 A 8.2 H 6.8 H 5 V/2 A 22 H 15 H 5 V/4 A 10 H 8.2 H
NOMINAL INDUCTOR VALUE
Inductor design is based on the assumption that the inductor ripple current is 30% of the maximum output dc current at a nominal 12 V input voltage. The inductor ripple current and inductance values are not critical, but are important in analyzing the trade-offs between cost, size, efficiency, and volume. The higher the ripple current, the lower the inductor size and volume. However, this leads to higher ac losses in the windings. Conversely, a higher inductor value means lower ripple current and smaller output filter capacitors, as well as slower transient response. The inductor design should be based on the maximum output current plus 15% (1/2 of the 30% ripple allowance) at the nominal input voltage:
INDUCTOR SELECTION
Once the value for the inductor is known, there are two ways to proceed: design the inductor in-house or buy the closest inductor that meets the overall design goals.
Standard Inductors
Buying a standard inductor provides the fastest, easiest solution. Many companies offer suitable power inductor solutions. A list of power inductor manufacturers is given in Table 7.
L 3 x (VIN ( NOM ) - VOUT ) x
VOUT f x IOUT ( MAX ) x VIN ( NOM )
(7)
Table 7. Recommended Inductor Manufacturers
Coilcraft Phone: 847/639-6400 Fax: 847/639-1469 Web: www.coilcraft.com SMT Power Inductors, Series 1608, 3308, 3316, 5022, 5022HC, DO3340, Low Cost Solution SMT Shielded Power Inductors Series DS5022, DS3316, DT3316, Best for Low EMI/RFI Power Inductors and Chokes, Series DC1012, PCV-0, PCV-1, PCV-2, PCH-27, PCH-45, Low Cost Coiltronics Phone: 561/241-7876 Fax: 561/241-9339 Web: www.coiltronics.com SMT Power Inductors, Series UNI-PAC2, UNI-PAC3 and UNI-PAC4, Low Cost Solution SMT Power Inductors, Series, ECONO-PAC, VERSA-PAC, Best for Low Profile or Flexible Design Power Inductors CTX Series, Low EMI/RFI, Low Cost Toroidal Inductors but not Miniature Murata Electronics North America, Inc. Phone: 770/436-1300 Fax: 770/436-3030 Web: www.murata.com SMT Power Inductors, Series LQT2535. Best for Low EMI/RFI
Chip Inductors LQN6C, LQS66C
Rev. A | Page 15 of 24
ADP3025
CIN AND COUT SELECTION
In continuous conduction mode, the source current of the upper MOSFET is approximately a square wave of duty cycle VOUT/VIN. To prevent large voltage transients, a low ESR input capacitor sized for the maximum rms current must be used. The maximum rms capacitor current is
IRMS = VOUT x (VIN - VOUT ) x
IOUT ( MAX ) VIN
Manufacturers such as Vishay, AVX, Elna, WIMA, and Sanyo provide good high performance capacitors. Sanyo's OSCON semiconductor dielectric capacitors have lower ESR for a given size, at a somewhat higher price. Choosing sufficient capacitors to meet the ESR requirement for COUT normally exceeds the amount of capacitance needed to meet the ripple current requirement. In surface-mount applications, multiple capacitors may have to be paralleled to meet the capacitance, ESR, or rms current handling requirements. Aluminum electrolytic and dry tantalum capacitors are available in surface-mount configurations. In the case of tantalum, it is critical that capacitors be surge tested for use in switching power supplies. Recommendations for output capacitors are shown in Table 8.
(8)
This formula has a maximum at VIN = 2 VOUT, where IRMS = IOUT(MAX)/2. Note that the capacitor manufacturer's ripple current ratings are often based on only 2,000 hours of life. Therefore, the user should further derate the capacitor, or choose one rated at a higher temperature than required. Several capacitors may be paralleled to meet size or height requirements in the design. If electrolytic or tantalum capacitors are used, an additional 0.1 F to 1 F ceramic bypass capacitor should be placed in parallel with CIN. The selection of COUT is driven by the required effective series resistance (ESR) and the desired output ripple. A good practice is to limit the ripple voltage to 1% of the nominal output voltage. It is assumed that the total ripple is caused by two factors: 25% comes from the COUT bulk capacitance value, and 75% comes from the capacitor ESR. The value of COUT can be determined by
POWER MOSFET SELECTION
N-channel power MOSFETs must be selected for use with the ADP3025 for the main and synchronous switches. The main selection parameters for the power MOSFETs are the threshold voltage (VGS(TH)) and on resistance (RDS(ON)). An internal LDO generates a 5 V supply that is boosted above the input voltage by using a bootstrap circuit. This floating 5 V supply is used for the upper MOSFET gate drive. Logic-level threshold MOSFETs must be used for both the main and synchronous switches. Maximum output current (IMAX) determines the RDS(ON) requirement for the two power MOSFETs. When the ADP3025 is operating in continuous mode, the simplifying assumption can be made that one of the two MOSFETs is always conducting the load current. The duty cycles for the MOSFETs are given by Upper MOSFET Duty Cycle = Lower MOSFET Duty Cycle = VOUT VIN VIN - VOUT VIN (11) (12)
C OUT =
IRIPPLE 2 x f x VRIPPLE
(9)
where IRIPPLE = 0.3 IOUT and VRIPPLE = 0.01 VOUT. The maximum acceptable ESR of COUT can then be found using
VRIPPLE ESR 0.75 x IRIPPLE (10)
Table 8. Recommended Capacitor Manufacturers
Maximum Output Current Input Capacitors 2A TOKIN Multilayer Ceramic Caps, 22 F/25 V P/N: C55Y5U1E226Z TAIYO YUDEN INC. Ceramic Caps, Y5V Series 10 F/25 V P/N: TMK432BJ106KM SANYO POSCAP TPC Series, 68 F/10 V SANYO POSCAP TPC Series, 68 F/10 V 4A TOKIN Multilayer Ceramic Caps, 2 x 22 F/25 V P/N: C55Y5U1E226Z TAIYO YUDEN INC. Ceramic Caps, Y5V Series 2 x 10 F/25 V P/N: TMK432BJ106KM SANYO POSCAP TPC Series, 2 x 68 F/10 V SANYO POSCAP TPC Series, 2 x 68 F/10 V
Output Capacitors 3.3 V Output Output Capacitors 5 V Output
Rev. A | Page 16 of 24
ADP3025
From the duty cycle, the required minimum RDS(ON) for each MOSFET can be derived by the following equations: Upper MOSFET:
RDS(ON ) (UPPER) = VIN x PD VOUT x IMAX 2 x (1 + T )
SOFT START
The soft start time of each of the switching regulators can be programmed by connecting a soft start capacitor to the corresponding soft start pin (SS3 or SS5). The time it takes each regulator to ramp up to its full duty ratio depends proportionally on the values of the soft start capacitors. The charging current is 2.5 A 20%. The capacitor value to set a given soft start time, tSS, is given by CSS 2.5 A x t SS (s ) (pF) 1. 8 V (17)
(13)
Lower MOSFET:
RDS(ON ) (LOWER) =
VIN x PD (VIN - VOUT ) x I MAX 2 x (1 + T )
(14)
where PD is the allowable power dissipation and is the temperature dependency of RDS(ON). PD is determined by efficiency and/or thermal requirements (see the Efficiency Enhancement section). (1 + T) is generally given for a MOSFET in the form of a normalized RDS(ON) versus temperature curve, but = 0.007/C can be used as an approximation for low voltage MOSFETs. Maximum MOSFET power dissipation occurs at maximum output current and can be calculated as follows: Upper MOSFET:
PD (UPPER) = Lower MOSFET: PD (LOWER) = VIN - VOUT x IMAX 2 x RDS(ON ) x (1 + T ) VIN (16) VOUT x IMAX 2 x RDS(ON ) x (1 + T ) VIN (15)
FIXED OR ADJUSTABLE OUTPUT VOLTAGE
Each of the ADP3025's switching controllers can be programmed to operate with a fixed or adjustable output voltage. As shown in Figure 17, putting the ADP3025 into fixed mode gives a nominal output of 3.3 V and 5 V for the two switching buck converters. By using two identical resistor dividers per converter, any output voltage between 800 mV and 6.0 V can be set. The center point of one divider is connected to the feedback pin, FB, and the center point of the other identical divider is connected to EAN. It is important to use 1% resistors. 10 k, 1% is a good value for the lower leg resistors. In this case, the upper leg resistors for a given output voltage is determined by
RUPPER =
VOUT - 0.8 V 0.08
(k )
(18)
Table 10 shows the resistor values for the most common output voltages.
Table 10. Typical Feedback Resistor Values
VOUT RUPPER RLOWER 1.5 V 9.1 k 10 k 1.8 V 13 k 10 k 2.5 V 22 k 10 k
The Schottky diode, D1 in Figure 17, conducts only during the dead time between conduction of the two power MOSFETs. D1's purpose is to prevent the body diode of the lower Nchannel MOSFET from turning on and storing charge during the dead time, which could cost as much as 1% in efficiency. D1 should be selected for forward voltage of less than 0.5 V when conducting IMAX. Recommended transistors for upper and lower MOSFETs are given in Table 9.
EFFICIENCY ENHANCEMENT
The efficiency of each switching regulator is inversely proportional to the losses during the switching conversion. The main factors to consider when attempting to maximize efficiency are 1. Resistive losses, which include the RDS(ON) of upper and lower MOSFETs, trace resistances, and output choke wire resistance. These losses contribute a major part of the overall power loss in low voltage battery-powered applications. However, trying to reduce these resistive losses by using multiple MOSFETs and thick traces may lead to lower efficiency and higher price. This is due to the trade-off between reduced resistive loss and increased gate drive loss that must be considered when optimizing efficiency.
Table 9. Recommended MOSFETs
Maximum Output Vishay/Siliconix International Rectifier 2A Si4412DY, 28 m IRF7805, 11 m 4A Si4410DY, 13.5 m IRF7811, 8.9 m RF7805, 11 m
Rev. A | Page 17 of 24
ADP3025
2. Switching losses due to the limited time of switching transitions. This occurs due to gate drive losses of the upper and lower MOSFETs and the switching node capacitive losses, and through hysteresis and eddy-current losses in power choke. Input and output capacitor ripple current losses should also be considered switching losses. These losses are input voltage dependent and can be estimated as follows:
PSWLOSS = VIN 1.85 x IMAX x CSN x f
FB, via an internal resistor. The error amplifier creates the closed-loop voltage level for the pulse-width modulator that drives the external power MOSFETs. The output LC filter smoothes the pulse-width modulated input voltage to a dc output voltage. The pulse-width modulator transfer function is VOUT/VEAOUT, where VEAOUT is the output voltage of the error amplifier. That function is dominated by the impedance of the output filter with its double-pole resonance frequency (fLC), a single zero at the output capacitor (fESR), and the dc gain of the modulator; it is equal to the input voltage divided by the peak ramp height (VRAMP), which is equal to 1.2 V when VIN = 12 V.
fLC = 1 2 x LF x COUT (20)
(19)
where CSN is the overall capacitance of the switching node related to loss. 3. Supply current of the switching controller (independent of the input current redirected to supply the MOSFETs' gates). This is a very small portion of the overall loss, but it does increase with input voltage.
fESR =
TRANSIENT RESPONSE CONSIDERATIONS
Both stability and regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in output load current. When a load step occurs, output voltage shifts by an amount equal to the current step multiplied by the total ESR of the summed output capacitor array. Output overshoot or ringing during the recovery time (in both directions of the current step change) indicates a stability problem. The external feedback compensation components shown in Figure 17 should provide adequate compensation for most applications.
ADP3025
PWM COMPARATOR VRAMP DRVL C2 EAO C1 R2 EAN R1 FB C3
02699-0-019
1 2 x ESR x C OUT
(21)
The compensation network consists of the internal error amplifier and two external impedance networks, ZIN and ZFB. Once the application and the output filter capacitance and ESR are chosen, the specific component values of the external impedance networks, ZIN and ZFB, can be determined. There are two design criteria for achieving stable switching regulator behavior within the line and load range. One is the maximum bandwidth of the loop, which affects fast transient response, if needed; the other is the minimum accepted by the design phase margin. The phase margin is the difference between the closed-loop phase and 180. Recommended phase margin is 45 to 60 for most applications.
VIN
DRVH L1 VOUT COUT
The equations to calculate the compensation poles and zeros are
fP 1 =
PARASITIC ESR
1 2 x R 2 x
C1 x C 2 C1 + C 2
(22)
fP 2 =
R3
1 2 x R3 x C 3 1 2 x R 2 x C1 1 2 x (R1 x R 3 ) x C 3
(23)
REF
fZ 1 =
(24)
Figure 18. Buck Regulator Voltage Control Loop
FEEDBACK LOOP COMPENSATION
The ADP3025 uses voltage mode control to stabilize the switching controller outputs. Figure 18 shows the voltage mode control loop for one of the buck switching regulators. The internal reference voltage, VREF, is applied to the positive input of the internal error amplifier. The other input of the error amplifier is EAN, and is internally connected to the feedback sensing pin,
fZ 2 =
(25)
The value of the internal resistor R1 is 74 k for the 3.3 V switching regulator and 130 k for the 5 V switching regulator.
Rev. A | Page 18 of 24
ADP3025
COMPENSATION LOOP DESIGN AND TEST METHOD
1. 2. 3. 4. 5. 6. 7. Choose the gain (R2/R1) for the desired bandwidth. Place fZ1 20% to 30% below fLC. Place fZ2 20% to 30% above fLC. Place fP1 at fESR. Check the output capacitor for worst-case ESR tolerances. Place fP2 at 40% to 60% of the oscillator frequency. Estimate phase margins in full frequency range (zero frequency to zero gain crossing frequency). Apply the designed compensation and test the transient response under a moderate step load change (30% to 60%) and various input voltages. Monitor the output voltage via an oscilloscope. The voltage overshoot or undershoot should be within 1% to 3% of the nominal output, without ringing and abnormal oscillation. 4. 3. 2. Whenever high currents must be routed between PCB layers, vias should be used liberally to create several parallel current paths so that the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. The power and ground planes should overlap each other as little as possible. It is generally easiest (although not necessary) to have the power and signal ground planes on the same PCB layer. The planes should be connected nearest to the first input capacitor where the input ground current flows from the converter back to the battery. If critical signal lines (including the voltage and current sense lines of the ADP3025) must cross through power circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier. The PGND1and PGND2 pins of the ADP3025 should connect first to a ceramic bypass capacitor on the VIN pin and then to the power ground plane, using the shortest possible trace. However, the power ground plane should not extend under other signal components, including the ADP3025 itself. If necessary, follow the preceding guideline to use the signal plane as a shield between the power ground plane and the signal circuitry. The AGND pin of the ADP3025 should connect first to the REF capacitor, and then to the signal ground plane. In cases where no signal ground plane can be used, short interconnections to other signal ground circuitry in the power converter should be used. The output capacitors of the power converter should be connected to the signal ground plane even though power current flows in the ground of these capacitors. For this reason, it is advisable to avoid critical ground connections (e.g., the signal circuitry of the power converter) in the signal ground plane between the input and output capacitors. It is also advisable to keep the planar interconnection path short (i.e., have input and output capacitors close together). The output capacitors should also be connected as close as possible to the load (or connector) that receives the power. If the load is distributed, the capacitors should also be distributed, generally in proportion to where the load tends to be more dynamic. Absolutely avoid crossing any signal lines over the switching power path loop, described in the Power Circuitry section.
5.
RECOMMENDED APPLICATIONS
1. ADP3025's switching channels are recommended to generate output current no greater than 5 A each. The maximum current output capability is subject to the limitation of ADP3025's gate driving capability and its maximum voltage rating. For a system with input voltage up to 20 V, the ADP3025 can be used to generate 5 V/3.3 V system power rails at 200 kHz. Switching frequency of 300 kHz is not recommended because the worst-case on time of the top MOSFET is too narrow (~500 ns), leaving no room for current sensing. For applications that use the silver box's 12 V rail as the input source, the ADP3025 can be configured to generate 5 V/3.3 V rails at both 200 kHz and 300 kHz. 6.
2.
3.
7.
LAYOUT CONSIDERATIONS
The following guidelines are recommended for optimal performance of a switching regulator in a portable PC system:
General Recommendations
1. For best results, a (minimum) 4-layer PCB is recommended. This should allow the needed versatility for control circuitry interconnections with optimal placement, a signal ground plane, power planes for both power ground and the input power, and wide interconnection traces in the rest of the power delivery current paths. Each square unit of 1 oz. copper trace has a resistance of ~0.53 m at room temperature. 8.
9.
Rev. A | Page 19 of 24
ADP3025
Power Circuitry
10. The switching power path should be routed on the PCB to encompass the smallest possible area in order to minimize radiated switching noise energy (i.e., EMI). Failure to take proper precautions often results in EMI problems for the entire PC system as well as noise-related operational problems in the power converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors, the two FETs (and the power Schottky diode, if used), including all interconnecting PCB traces and planes. The use of short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing, and it accommodates high current demand with minimal voltage loss. 11. A power Schottky diode (1 A ~ 2 A dc rating) placed from the lower FET's source (anode) to drain (cathode) helps to minimize switching power dissipation in the upper FET. In the absence of an effective Schottky diode, this dissipation occurs through the following sequence of switching events. The lower FET turns off in advance of the upper FET turning on (necessary to prevent cross-conduction). The circulating current in the power converter, no longer finding a path for current through the channel of the lower FET, draws current through the inherent body drain diode of the FET. The upper FET turns on, and the reverse recovery characteristic of the lower FET's body drain diode prevents the drain voltage from being pulled high quickly. The upper FET then conducts very large current while it momentarily has a high voltage forced across it, which translates into added power dissipation in the upper FET. The Schottky diode minimizes this problem by carrying a majority of the circulating current when the lower FET is turned off, and by virtue of its essentially nonexistent reverse recovery time. 12. Whenever a power dissipating component (e.g., a power MOSFET) is soldered to a PCB, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. Two important reasons for this are: improved current rating through the vias (if it is a current path) and improved thermal performance, especially if the vias are extended to the opposite side of the PCB where a plane can more readily transfer the heat to the air. 13. The output power path, though not as critical as the switching power path, should also be routed to encompass a small area. The output power path is formed by the current path through the inductor, the output capacitors, and back to the input capacitors. 14. For best EMI containment, the power ground plane should extend fully under all the power components except the output capacitors. These are the input capacitors, the power MOSFETs and Schottky diode, the inductor, and any snubbing elements that might be added to dampen ringing. Avoid extending the power ground under any other circuitry or signal lines, including the voltage and current sense lines.
Signal Circuitry
15. The CS and SW traces should be Kelvin-connected to the upper MOSFET drain and source so that the additional voltage drop due to current flow on the PCB at the current sense comparator connections does not affect the sensed voltage. It is desirable to have the ADP3025 close to the output capacitor bank and not in the output power path so that any voltage drop between the output capacitors and the AGND pin is minimized and voltage regulation is not compromised.
Rev. A | Page 20 of 24
ADP3025 OUTLINE DIMENSIONS
9.80 9.70 9.60
38
20
4.50 4.40 4.30 6.40 BSC
1 19
PIN 1 1.20 MAX 8 0
0.15 0.05 COPLANARITY 0.10 0.50 BSC 0.27 0.17
SEATING PLANE
0.20 0.09
0.70 0.60 0.45
COMPLIANT TO JEDEC STANDARDS MO-153BD-1
Figure 19. 38-Lead Thin Shrink Small Outline Package [TSSOP] (RU-38) Dimensions shown in millimeters
ORDERING GUIDE
Model ADP3025JRU-REEL Temperature Range 0C to 70C Package Description Thin Shrink Small Outline (TSSOP) Package Option RU-38
Rev. A | Page 21 of 24
ADP3025 NOTES
Rev. A | Page 22 of 24
ADP3025 NOTES
Rev. A | Page 23 of 24
ADP3025 NOTES
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02699-0-4/04(A)
Rev. A | Page 24 of 24

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